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56f800 16-bit digital signal controllers freescale.com 56F803 data sheet preliminary technical data dsp56F803 rev. 16 09/2007
document revision history version history description of change rev. 16 added revision history. added this text to footnote 2 in table 3-8 : ?however, the high pulse width does not have to be any particular percent of the low pulse width.?
56F803 technical data, rev. 16 freescale semiconductor 3 56F803 block diagram jtag/ once port digital reg analog reg low voltage supervisor program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit pll clock gen 16-bit 56800 core pab pdb xdb2 cgdb xab1 xab2 xtal extal interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset reset irqa irqb applica- tion-specific memory & peripherals interrupt controller program memory 32252 x 16 flash 512 x 16 sram boot flash 2048 x 16 flash data memory 4096 x 16 flash 2048 x 16 sram cop/ watchdog spi or gpio sci or gpio quad timer d a/d1 a/d2 adc 4 2 2 4 4 3 6 pwm outputs fault inputs pwma 16 16 vcapc v dd v ss v dda v ssa 6 26 6* ? ? ? ? ? ? ? ? extboot current sense inputs 3 quadrature decoder 0 / quad timer a can 2.0a/b 2 clko external address bus switch bus control external data bus switch external bus interface unit rd enable wr enable ds select ps select 10 16 6 a[00:05] d[00:15] a[06:15] or gpio-e2:e3 & gpio-a0:a7 4 quad timer c vref quad timer b * includes tcs pin which is reserv ed for factory use and is tied to vss 56F803 general description ? up to 40 mips at 80mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? hardware do and rep loops ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ? 31.5k 16-bit words (64kb) program flash ?512 16-bit words (1kb) program ram ?4k 16-bit words (8kb) data flash ?2k 16-bit words (4kb) data ram ?2k 16-bit words (4kb) boot flash ? up to 64k 16-bit words each of external program and data memory ? 6-channel pwm module ? two 4-channel 12-bit adcs ? quadrature decoder ? can 2.0 b module ? serial communication interface (sci) ? serial peripheral interface (spi) ? up to two general purpose quad timers ? jtag/once tm port for debugging ? 16 shared gpio lines ? 100?pin lqfp package
56F803 technical data, rev. 16 4 freescale semiconductor part 1 overview 1.1 56F803 features 1.1.1 processing core ? efficient 16-bit 56800 family controller engine with dual harvard architecture ? as many as 40 million instructions pe r second (mips) at 80mhz core frequency ? single-cycle 16 16 - bit parallel multiplier- accumulator (mac) ?two 36 - bit accumulators, incl uding extension bits ?16 - bit bidirectional barrel shifter ? parallel instruction set with un ique processor addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stac k with depth limited only by memory ? jtag/once debug programming interface 1.1.2 memory ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low-cost, high-volume flash solution ?31.5k 16-bit words of program flash ?512k 16 - bit words of program ram ?4k 16 - bit words of data flash ?2k 16 - bit words of data ram ?2k 16 - bit words of boot flash ? off-chip memory expansion ca pabilities programmable for 0, 4, 8, or 12 wait states ? as much as 64k 16 bits of data memory ? as much as 64k 16 bits of program memory 1.1.3 peripheral circuits for 56F803 ? pulse width modulator module (pwm) with six pwm ou tputs, three current sens e inputs, and three fault inputs, fault-tolerant design with dead time insertion, supports both center- and edge- aligned modes, supports freescale?s patented dead time distortion correction ?two 12 - bit analog-to-digital converters (adcs), whic h support two simultaneous conversions; adc and pwm modules can be synchronized ? quadrature decoder with four inputs (shares pins with quad timer)
56F803 description 56F803 technical data, rev. 16 freescale semiconductor 5 ? four general purpose quad timers: ti mer a (sharing pins with quad dec0 ), timers b &c without external pins and timer d with two pins ? can 2.0 b module with 2-pin ports for transmit and receive ? serial communication interface (sci) with two pins (or two additional gpio lines) ? serial peripheral interface (spi) with configur able 4-pin port (or four additional gpio lines) ? computer operating properly (cop) watchdog timer ? two dedicated external interrupt pins ? sixteen multiplexed genera l purpose i/o (gpio) pins ? external reset input pi n for hardware reset ? jtag/on-chip emulation (once?) for unobtrusi ve, processor speed-ind ependent debugging ? software-programmable, phase locked loop-based frequency synthesizer for the controller core clock 1.1.4 energy information ? fabricated in high-density cmos with 5v - tolerant, ttl-compatible digital inputs ? uses a single 3.3v power supply ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available 1.2 56F803 description the 56F803 is a member of the 56800 core-based family of processors. it combines, on a single chip, the processing power of a dsp and the func tionality of a microcont roller with a flexible set of peripherals to create an extremely cost-effective so lution. because of its low cost, conf iguration flexibility, and compact program code, the 56F803 is well-suited for ma ny applications. the 56F803 includes many peripherals that are especially useful for app lications such as motion control, sm art appliances, st eppers, encoders, tachometers, limit switch es, power supply and contro l, automotive control, engine management, noise suppression, remote utility mete ring, and industrial control for power, lighting, and automation. the 56800 core is based on a harvard-style architectur e consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the mcu-style programming model and optimized instruction set allow stra ightforward generation of efficient, compact de vice and control code. the instruction set is also highly efficient for c compilers to enab le rapid development of optimized control applications. the 56F803 supports program executi on from either internal or extern al memories. two data operands can be accessed from the on-ch ip data ram per instruction cycle. the 56F803 also provides two external dedicated interrupt lines, and up to 16 general purpose input/output (gpi o) lines, depending on peripheral configuration. the 56F803 controller include s 31.5k words (16-bit) of program flash and 4k words of data flash (each programmable through the jtag port) with 512 words of program ram a nd 2k words of data ram. it also supports program execu tion from external memory. a total of 2k words of boot flas h is incorporated for easy custom er-inclusion of field-programmable
56F803 technical data, rev. 16 6 freescale semiconductor software routines that can be us ed to program the main program and data flas h memory areas. both program and data flash memori es can be independently bulk ? erased or erased in page sizes of 256 words. the boot flash memory can al so be either bulk- or page - erased. a key application-specific feature of the 56F803 is the inclusion of a puls e width modulator (pwm) module. this module incorporates three compleme ntary, individually progra mmable pwm signal outputs (the module is also capable of supporting three independent pwm f unctions, for a total of six pwm outputs) to enhance motor control functionality. complementary operation pe rmits programmable dead time insertion, distortion correcti on via current sensing by software, and separate top and bottom output polarity control. the up-counter value is progr ammable to support a cont inuously variable pwm frequency. edge- and center-aligned synchronous pul se width control (0% to 100% modulation) is supported. the device is ca pable of controlling most motor type s: acim (ac induction motors), both bdc and bldc (brush and brushl ess dc motors), srm and vrm (s witched and variable reluctance motors), and stepper motors. the pwm incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capabi lity to directly drive standard opto-isolators. a ?smoke-inhibit?, write-once protection feature for key parameters and patented pw m waveform distortion correction circuit are also provided. the pwm is double-buffered and incl udes interrupt controls to permit integral reload rates to be programmab le from 1 to 16. the pwm modul e provides a reference output to synchronize the adc. the 56F803 incorporates a separate quadrature decoder capable of cap turing all four transitions on the two-phase inputs, permitting genera tion of a number proportional to actu al position. speed computation capabilities accommodate both fast and slow moving shafts. the integrated watchdog timer in the quadrature decoder can be programmed with a time-out value to alarm when no shaft motion is detected. each input is filtered to ensure only true transitions are recorded. this controller also provides a full set of stan dard programmable periphera ls that include a serial communications interface (sci), one serial peripheral interface (spi), and four quad timers. any of these interfaces can be used as ge neral purpose input/outputs (gpio) if that function is not required. a controller area network interface (can version 2.0 a/b-compliant) and an internal interrupt controller are also included on the 56F803. 1.3 state of the art development environment ? processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software ap plication creation with an expert knowledge system. ? the code warrior integrated development environm ent is a sophisticated to ol for code navigation, compiling, and debugging. a complete set of eval uation modules (evms) and development system cards will support concurrent engineering. together, pe, code warrior and evms create a complete, scalable tools solution for easy, fast, and efficient development.
product documentation 56F803 technical data, rev. 16 freescale semiconductor 7 1.4 product documentation the four documents listed in table 1-1 are required for a complete desc ription and proper design with the 56F803. documentation is available from local freescale distributor s, freescale semiconductor sales offices, freescale literature distribution centers, or online at: www.freescale.com table 1-1 56F803 chip documentation 1.5 data sheet conventions this data sheet uses the following conventions: topic description order number 56800e family manual detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set 56800efm dsp56f801/803/805/807 user?s manual detailed description of memory, peripherals, and interfaces of the 56f801, 56F803, 56F803, and 56f807 dsp56f801-7um 56F803 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) dsp56F803 56F803 errata details any chip issues that might be present dsp56F803e overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
56F803 technical data, rev. 16 8 freescale semiconductor part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56F803 are organized into functional groups, as shown in table 2-1 and as illustrated in figure 2-1 . in table 2-2 through table 2-17 , each table row describes the signal or signals present on a pin. table 2-1 functional group pin allocations functional group number of pins detailed description power (v dd or v dda )7 table 2-2 ground (v ss or v ssa )7 table 2-3 supply capacitors 2 table 2-4 pll and clock 3 table 2-5 address bus 1 16 table 2-6 data bus 16 table 2-7 bus control 4 table 2-8 interrupt and program control 4 table 2-9 pulse width modulator (pwm) port 12 table 2-10 serial peripheral interface (spi) port 1 1. alternately, gpio pins 4 table 2-11 quadrature decoder port 2 2. alternately, quad timer pins 4 table 2-12 serial communications interface (sci) port 1 2 table 2-13 can port 2 table 2-14 analog to digital converter (adc) port 9 table 2-15 quad timer module port 2 table 2-16 jtag/on-chip emulation (once) 6 table 2-17
introduction 56F803 technical data, rev. 16 freescale semiconductor 9 figure 2-1 56F803 signals iden tified by functional group 1 1. alternate pin functionality is shown in parenthesis. 56F803 power port ground port power port ground port pll and clock external address bus or gpio external data bus external bus control sci0 port or gpio v dd v ss v dda v ssa vcapc extal xtal clko a0-a5 a6-7 (gpioe2-e3) a8-15 (gpioa0-a7) d0?d15 ps ds rd wr phasea0 (ta0) phaseb0 (ta1) index0 (ta2) home0 (ta3) tck tms tdi tdo trst de quadrature decoder or quad timer a jtag/once ? port pwma0-5 isa0-2 faulta0-2 sclk (gpioe4) mosi (gpioe5) miso (gpioe6) ss (gpioe7) txd0 (gpioe0) rxd0 (gpioe1) ana0-7 vref mscan_rx mscan_tx td1-2 irqa irqb reset extboot quad timer d adca port other supply ports 6 6* 1 1 2 1 1 1 6 2 8 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 interrupt/ program control 6 3 3 1 1 1 1 1 1 8 1 1 1 2 1 1 1 1 pwma port spi port or gpio can * includes tcs pin which is reserv ed for factory use and is tied to vss
56F803 technical data, rev. 16 10 freescale semiconductor 2.2 power and ground signals table 2-2 power inputs no. of pins signal na me signal description 6 v dd power ?these pins provide power to the internal structures of the chip, and should all be attached to v dd. 1 v dda analog power ?this pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3v supply. table 2-3 grounds no. of pins signal name signal description 5 v ss gnd ?these pins provide grounding for the inter nal structures of the chip, and should all be attached to v ss. 1 v ssa analog ground ?this pin supplies an analog ground. 1 tcs tcs ?this schmitt pin is reserved for factory use and must be tied to v ss for normal use. in block diagrams, this pin is considered an additional v ss. table 2-4 supply capacitors no. of pins signal name signal type state during reset signal description 2 vcapc supply supply vcapc ?connect each pin to a 2.2 f or greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). for more info rmation, please refer to section 5.2 .
clock and phase locked loop signals 56F803 technical data, rev. 16 freescale semiconductor 11 2.3 clock and phase locked loop signals 2.4 address, data, and bus control signals table 2-5 pll and clock no. of pins signal name signal type state during reset signal description 1 extal input input external crystal oscillator input ?this input should be connected to an 8mhz external crystal or cerami c resonator. for mo re information, please refer to section 3.5 . 1 xtal input/ output chip-driven crystal oscillator output ?this output should be connected to an 8mhz external crystal or ceramic resonator. for more information, please refer to section 3.5 . this pin can also be connected to an external clock source. for more information, please refer to section 3.5.3 . 1 clko output chip-driven clock output ?this pin outputs a buffered clock signal. by programming the clkosel [4:0] bits in the clko select register (clkosr), the user can select between outputting a version of the signal applied to xtal and a version of the device?s master clock at the output of the pll. the clock frequency on this pin can also be disabled by programming the clkosel[4:0] bits in clkosr. table 2-6 address bus signals no. of pins signal name signal type state during reset signal description 6 a0?a5 output tri-stated address bus ?a0?a5 specify the address for external program or data memory accesses. 2 a6?a7 gpioe2 ? gpioe3 output input/o utput tri-stated input address bus ?a6?a7 specify the address for external program or data memory accesses. port e gpio ?these two pins are general purpose i/o (gpio) pins that can be individually programmed as input or output pins. after reset, the default state is address bus. 8 a8?a15 gpioa0 ? gpioa7 output input/o utput tri-stated input address bus ?a8?a15 specify the address for external program or data memory accesses. port a gpio ?these eight pins are general purpose i/o (gpio) pins that can be individually progra mmed as input or output pins. after reset, the default state is address bus.
56F803 technical data, rev. 16 12 freescale semiconductor 2.5 interrupt and program control signals table 2-7 data bus signals no. of pins signal name signal type state during reset signal description 16 d0?d15 input/o utput tri-stated data bus ? d0?d15 specify the data for external program or data memory accesses. d0?d15 are tri- stated when the external bus is inactive. internal pul l-ups may be active. table 2-8 bus control signals no. of pins signal name signal type state during reset signal description 1 ps output tri-stated program memory select ?ps is asserted low for external program memory access. 1 ds output tri-stated data memory select ?ds is asserted low for external data memory access. 1 wr output tri-stated write enable ?wr is asserted during external memory write cycles. when wr is asserted low, pins d0?d15 become outputs and the device puts data on the bus. when wr is deasserted high, the external data is latched inside the external device. when wr is asserted, it qualifies the a0?a15, ps , and ds pins. wr can be connected directly to the we pin of a static ram. 1 rd output tri-stated read enable ?rd is asserted during external memory read cycles. when rd is asserted low, pins d0?d15 become inputs and an external device is enabled onto the device data bus. when rd is deasserted high, the external data is latched inside the controller. when rd is asserted, it qualifies the a0?a15, ps , and ds pins. rd can be connected directly to the oe pin of a static ram or rom. table 2-9 interrupt and program control signals no. of pins signal name signal type state during reset signal description 1 irqa input (schmitt) input external interrupt request a ?the irqa input is a synchronized external interrupt request indicating an external device is requesting service. it can be programmed to be level-sensitive or negative-edge- triggered. 1 irqb input (schmitt) input external interrupt request b ?the irqb input is an external interrupt request indicating an external device is requesting service. it can be programmed to be level-sensitive or negative-edge-triggered.
pulse width modulator (pwm) signals 56F803 technical data, rev. 16 freescale semiconductor 13 2.6 pulse width modulator (pwm) signals 1 reset input (schmitt) input reset ?this input is a direct hardware reset on the processor. when reset is asserted low, the controller is initialized and placed in the reset state. a schmitt trigge r input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the extboot pin. the internal reset signal will be deasserted synchronous with the internal cl ocks, after a fixed number of internal clocks. to ensure a complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the once/jta g module. in this case, assert reset , but do not assert trst . 1 extboot input (schmitt) input external boot ?this input is tied to v dd to force device to boot from off-chip memory. otherwise, it is tied to v ss . table 2-10 pulse width m odulator (pwma) signals no. of pins signal name signal type state during reset signal description 6 pwma0 ? 5 output tri-stated pwma0 ? 5 ? these are six pwma output pins. 3 isa0 ? 2 input (schmitt) input isa0 ? 2 ? these three input current status pins are used for top/bottom pulse width correction in complementary channel operation for pwma. 3 faulta0 ? 2 input (schmitt) input faulta0 ? 2 ? these three fault input pins are used for disabling selected pwma outputs in cases where fault conditions originate off-chip. table 2-9 interrupt and progra m control signals (continued) no. of pins signal name signal type state during reset signal description
56F803 technical data, rev. 16 14 freescale semiconductor 2.7 serial peripheral interface (spi) signals table 2-11 serial peripher al interface (spi) signals no. of pins signal name signal type state during reset signal description 1 miso gpioe6 input/out put input/out put input input spi master in/slave out (miso) ?this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high impedance state if the slave device is not selected. port e gpio ?this general purpose i/o (gpio) pin can be individually programmed as an input or output pin. after reset, the defau lt state is miso. 1 mosi gpioe5 input/out put input/out put input input spi master out/slave in (mosi) ?this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. port e gpio ?this general purpose i/o (gpio) pin can be individually programmed as an input or output pin. after reset, the defau lt state is mosi. 1 sclk gpioe4 input/out put input/out put input input spi serial clock ?in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. port e gpio ?this general purpose i/o (gpio) pin can be individually programmed as an input or output pin. after reset, the default state is sclk. 1 ss gpioe7 input input/out put input input spi slave select ?in master mode, this pi n is used to arbitrate multiple masters. in slave mode, this pin is used to select the slave. port e gpio ?this general purpose i/o (gpio) pin can be individually programmed as an input or output pin. after reset, the default state is ss .
quadrature decoder signals 56F803 technical data, rev. 16 freescale semiconductor 15 2.8 quadrature decoder signals 2.9 serial communications interface (sci) signals table 2-12 quadrature dec oder (quad dec0) signals no. of pins signal name signal type state during reset signal description 1 phasea0 ta0 input input/output input input phase a ?quadrature decoder #0 phasea input ta0 ?timer a channel 0 1 phaseb0 ta1 input input/output input input phase b ?quadrature decoder #0 phaseb input ta1 ?timer a channel 1 1 index0 ta2 input input/output input input index ?quadrature decoder #0 index input ta2 ?timer a channel 2 1 home0 ta3 input input/output input input home ?quadrature decoder #0 home input ta3 ?timer a channel 3 table 2-13 serial communicati ons interface (sci0) signals no. of pins signal name signal type state during reset signal description 1 txd0 gpioe0 output input/output input input transmit data (txd0) ?sci0 transmit data output port e gpio ?this general purpose i/o (gpio) pin can be individually programmed as an input or output pin. after reset, the default state is sci output. 1 rxd0 gpioe1 input input/output input input receive data (rxd0) ? sci0 receive data input port e gpio ?this general purpose i/o (gpio) pin can be individually programmed as an input or output pin. after reset, the default state is sci input.
56F803 technical data, rev. 16 16 freescale semiconductor 2.10 can signals 2.11 analog-to-digital converter (adc) signals 2.12 quad timer module signals table 2-14 can module signals no. of pins signal name signal type state during reset signal description 1 mscan_ rx input (schmitt) input mscan receive data ?this is the mscan input. this pin has an internal pull-up resistor. 1 mscan_ tx output output mscan transmit data ?mscan output. can output is open-drain output and a pull-up resistor is needed. table 2-15 analog to di gital converter signals no. of pins signal name signal type state during reset signal description 4 ana0 ? 3 input input ana0 ? 3 ?analog inputs to adc channel 1 4 ana4 ? 7 input input ana4 ? 7 ?analog inputs to adc channel 2 1 vref input input vref ?analog reference voltage for adc. must be set to v dda -0.3v for optimal performance. table 2-16 quad timer module signals no. of pins signal name signal type state during reset signal description 2 td1 ? 2 input/output input td1 ? 2 ? timer d channel 1 ? 2
jtag/once 56F803 technical data, rev. 16 freescale semiconductor 17 2.13 jtag/once part 3 specifications 3.1 general characteristics the 56F803 is fabricated in high-de nsity cmos with 5-v tolerant t tl-compatible digi tal inputs. the term ?5-v tolerant? refers to the capability of an i/o pin, built on a 3.3v-compatible process technology, to withstand a voltage up to 5.5v without damaging the devi ce. many systems have a mixture of devices designed for 3.3v and 5v power suppl ies. in such systems, a bus ma y carry both 3.3v and 5v-compatible i/o voltage levels (a standard 3.3v i/o is designed to rece ive a maximum voltage of 3.3v 10% during normal operation without causing damage ). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels wi thout being damaged. table 2-17 jtag/on-chip em ulation (once) signals no. of pins signal name signal type state during reset signal description 1 tck input (schmitt) input, pulled low internally test clock input ?this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/once port. the pin is connected internally to a pull-down resistor. 1 tms input (schmitt) input, pulled high internally test mode select input ?this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. note: always tie the tms pin to v dd through a 2.2k resistor. 1 tdi input (schmitt) input, pulled high internally test data input ?this input pin provides a serial input data stream to the jtag/once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdo output tri-stated test data output ?this tri-statable output pin pr ovides a serial output data stream from the jtag/once port. it is driven in the shift-ir and shift-dr controller states, and chan ges on the falling edge of tck. 1 trst input (schmitt) input, pulled high internally test reset ?as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted at power-up and whenever reset is asserted. the only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the once/jtag module. in this case, assert reset , but do not assert trst . note: for normal operation, connect trst directly to v ss . if the design is to be used in a debugging environment, trst may be tied to v ss through a 1k resistor. 1 de output output debug event ?de provides a low pulse on recognized debug events.
56F803 technical data, rev. 16 18 freescale semiconductor absolute maximum ratings given in table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the 56F803 dc/ac electrical specifi cations are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published af ter complete characterization a nd device qualificat ions have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 3-1 absolute maximum ratings characteristic symbol min max unit supply voltage v dd v ss ? 0.3 v ss + 4.0 v all other input voltages, excluding analog inputs v in v ss ? 0.3 v ss + 5.5v v voltage difference v dd to v dda v dd - 0.3 0.3 v voltage difference v ss to v ssa v ss - 0.3 0.3 v analog inputs ana0-7 and vref v in v ssa ? 0.3 v dda + 0.3 v analog inputs extal and xtal v in v ssa ? 0.3 v ssa + 3.0 v current drain per pin excluding v dd , v ss , pwm outputs, tcs, v pp , v dda , v ssa i?10ma table 3-2 recommended operating conditions characteristic symbol min typ max unit supply voltage, digital v dd 3.0 3.3 3.6 v supply voltage, analog v dda 3.0 3.3 3.6 v voltage difference v dd to v dda v dd -0.1 - 0.1 v
general characteristics 56F803 technical data, rev. 16 freescale semiconductor 19 notes: 1. theta-ja determined on 2s2p test boards is frequen tly lower than would be observed in an application. determined on 2s2p thermal test board. 2. junction to ambient ther mal resistance, theta-ja ( r ja ) was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural convection. theta-ja was also simulated on a thermal test board with two internal planes (2s2p where ?s? is the number of signal layers and ?p? is the number of planes) per jesd51-6 and je sd51-7. the correct name for theta-ja for for ced convection or with the non-single layer boards is theta-jma. 3. junction to case thermal resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate techniqu e with the cold plate temperature used as the ?case? temperature. the basic cold plate measurement technique is described by mil-std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance wh en the package is being used with a heat sink. voltage difference v ss to v ssa v ss -0.1 - 0.1 v adc reference voltage vref 2.7 ? v dda v ambient operating temperature t a ?40 ? 85 c table 3-3 thermal characteristics 6 characteristic comments symbol value unit notes 100-pin lqfp junction to ambient natural convection r ja 41.7 c/w 2 junction to ambient (@1m/sec) r jma 37.2 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma (2s2p) 34.2 c/w 1,2 junction to ambient (@1m/sec) four layer board (2s2p) r jma 32 c/w 1,2 junction to case r jc 10.2 c/w 3 junction to center of case jt 0.8 c/w 4, 5 i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd x v dd + p i/o )w junction to center of case p dmax (tj - ta) /r ja w7 table 3-2 recommended operating conditions characteristic symbol min typ max unit
56F803 technical data, rev. 16 20 freescale semiconductor 4. thermal characterization parameter, psi-jt ( jt ), is the ?resistance? from junction to re ference point thermocouple on top center of case as defined in jesd51-2. jt is a useful value to use to estimate junction temperature in steady stat e customer environments. 5. junction temperature is a function of on-chip power dissipation, package ther mal resistance, mount ing site (board) temperature, ambient temperature, air flow, power dissip ation of other components on the board, and board thermal resistance. 6. see section 5.1 from more details on thermal design considerations. 7. tj = junction temperature ta = ambient temperature 3.2 dc electrical characteristic table 3-4 dc electrical characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc 2.25 ? 2.75 v input low voltage (xtal/extal) v ilc 0?0.5v input high voltage (schmitt trigger inputs) 1 v ihs 2.2 ? 5.5 v input low voltage (schmitt trigger inputs) 1 v ils -0.3 ? 0.8 v input high voltage (all other digital inputs) v ih 2.0 ? 5.5 v input low voltage (all other digital inputs) v il -0.3 ? 0.8 v input current high (pullup/pulldown resistors disabled, v in =v dd ) i ih -1 ? 1 a input current low (pullup/pulldown resistors disabled, v in =v ss ) i il -1 ? 1 a input current high (with pullup resistor, v in =v dd )i ihpu -1 ? 1 a input current low (with pullup resistor, v in =v ss )i ilpu -210 ? -50 a input current high (with pulldown resistor, v in =v dd )i ihpd 20 ? 180 a input current low (with pulldown resistor, v in =v ss )i ilpd -1 ? 1 a nominal pullup or pulldown resistor value r pu , r pd 30 k output tri-state current low i ozl -10 ? 10 a output tri-state current high i ozh -10 ? 10 a
dc electrical characteristic 56F803 technical data, rev. 16 freescale semiconductor 21 input current high (analog inputs, v in =v dda ) 2 i iha -15 ? 15 a input current low (analog inputs, v in =v ssa ) 2 i ila -15 ? 15 a output high voltage (at ioh) v oh v dd ? 0.7 ? ? v output low voltage (at iol) v ol ??0.4 v output source current i oh 4??ma output sink current i ol 4??ma pwm pin output source current 3 i ohp 10 ? ? ma pwm pin output sink current 4 i olp 16 ? ? ma input capacitance c in ?8?pf output capacitance c out ?12? pf v dd supply current i ddt 5 run 6 ? 126 152 ma wait 7 ? 105 129 ma stop ? 60 84 ma low voltage interrupt, external power supply 8 v eio 2.4 2.7 3.0 v low voltage interrupt, internal power supply 9 v eic 2.0 2.2 2.4 v power on reset 10 v por ?1.72.0 v 1. 1. schmitt trigger inputs are: extboot, irqa , irqb , rese t, isa0-2, faulta0-3, tcs, tck, trst , tms, tdi, and mscan_rx 2. analog inputs are: ana[0:7], xtal and extal. specification assumes adc is not sampling. 3. pwm pin output source current measured with 50% duty cycle. 4. pwm pin output sink current m easured with 50% duty cycle. 5. i ddt = i dd + i dda (total supply current for v dd + v dda ) 6. run (operating) i dd measured using 8mhz clock source. all inputs 0. 2v from rail; outputs unloaded. all ports configured as inputs; measured with all modules enabled. 7. wait i dd measured using external square wave clock source (f osc = 8mhz) into xtal; all inputs 0.2v from rail; no dc loads; less than 50pf on all outputs. c l = 20pf on extal; all ports configured as inputs; extal capacitance linearly affects wait i dd ; measured with pll enabled. table 3-4 dc electrical characteristics (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min typ max unit
56F803 technical data, rev. 16 22 freescale semiconductor figure 3-1 maximum r un idd vs. frequency (see note 6. in table 3-14 ) 3.3 ac electrical characteristics timing waveforms in section 3.3 are tested using the v il and v ih levels specified in the dc characteristics table. in figure 3-2 the levels of v ih and v il for an input signal are shown. 8. this low-voltage interrupt monitors the v dda external power supply. v dda is generally connected to the same potential as v dd via separate traces. if v dda drops below v eio , an interrupt is generated. functi onality of the device is guaranteed under transient conditions when v dda > v eio (between the minimum specified v dd and the point when the v eio interrupt is generated). 9. this low voltage interrupt monitors the internally regulated core power supply. if the output from the internal voltage is regulator drops below v eic , an interrupt is generated. since the core logic s upply is internally regulated, this interrupt will not be generated unless the external power supply dr ops below the minimum specified value (3.0v). 10. power ? on reset occurs whenever the internally regulated 2.5v digital supply drops below 1.5v typical. while power is ramping up, this signal remains active as long as the internal 2.5v is below 1.5v typical, no matter how long the ramp-up rate is. the internally regulated voltage is typically 100mv less than v dd during ramp-up, until 2.5v is reached, at which time it self-regulates. 0 30 90 120 180 60 20 40 60 80 freq. (mhz) idd (ma) 150 idd digital idd analog idd total
flash memory characteristics 56F803 technical data, rev. 16 freescale semiconductor 23 figure 3-2 input signal measurement references figure 3-3 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 3-3 signal states 3.4 flash memory characteristics table 3-5 flash memory truth table mode xe 1 1. x address enable, all rows are disabled when xe = 0 ye 2 2. y address enable, ymux is disabled when ye = 0 se 3 3. sense amplifier enable oe 4 4. output enable, tri-state flash data out bus when oe = 0 prog 5 erase 6 mas1 7 nvstr 8 standby l l l l l l l l read hhhh l l l l word programhhllh llh page erase h l l l l h l h mass erase h l l l l h h h v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
56F803 technical data, rev. 16 24 freescale semiconductor 5. defines program cycle 6. defines erase cycle 7. defines mass erase cyc le, erase whole block 8. defines non-volatile store cycle table 3-6 ifren truth table mode ifren = 1 ifren = 0 read read information block read main memory block word program program information block program main memory block page erase erase information block erase main memory block mass erase erase both block e rase main memory block table 3-7 flash timing parameters operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit figure program time t prog* 20 ? ? us figure 3-4 erase time t erase* 20 ? ? ms figure 3-5 mass erase time t me* 100 ? ? ms figure 3-6 endurance 1 e cyc 10,000 20,000 ? cycles data retention 1 d ret 10 30 ? years the following parameters should only be used in the manual word programming mode prog/erase to n vstr set up time t nv* ?5?us figure 3-4 , figure 3-5 , figure 3-6 nvstr hold time t nvh* ?5?us figure 3-4 , figure 3-5 nvstr hold time (mass erase) t nvh1* ? 100 ? us figure 3-6 nvstr to program set up time t pgs* ?10?us figure 3-4 recovery time t rcv* ?1?us figure 3-4 , figure 3-5 , figure 3-6
flash memory characteristics 56F803 technical data, rev. 16 freescale semiconductor 25 figure 3-4 flash program cycle cumulative program hv period 2 t hv ?3?ms figure 3-4 program hold time 3 t pgh ??? figure 3-4 address/data set up time 3 t ads ??? figure 3-4 address/data hold time 3 t adh ??? figure 3-4 1. one cycle is equal to an erase program and read. 2. thv is the cumulative high voltage programming time to the same row before next erase. the same address cannot be programmed twice before next erase. 3. parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *the flash interface unit provides regist ers for the control of these parameters. table 3-7 flash timing parameters (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit figure xadr yadr ye din prog nvstr tnvs tpgs tadh tprog tads tpgh tnvh trcv thv ifren xe
56F803 technical data, rev. 16 26 freescale semiconductor figure 3-5 flash erase cycle figure 3-6 flash ma ss erase cycle xadr ye=se=oe=mas1=0 erase nvstr tnvs tnvh trcv terase ifren xe xadr ye=se=oe=0 erase nvstr tnvs tnvh1 trcv tme mas1 ifren xe
external clock operation 56F803 technical data, rev. 16 freescale semiconductor 27 3.5 external clock operation the 56F803 system clock can be deri ved from an external crystal or an external system clock signal. to generate a reference frequency using the internal oscillator, a reference crystal must be connected between the extal and xtal pins. 3.5.1 crystal oscillator the internal oscillator is also designed to interfac e with a parallel-resonant crystal resonator in the frequency range specified fo r the external crystal in table 3-9 . in figure 3-7 a recommended crystal oscillator circuit is s hown. follow the crystal supplier?s reco mmendations when selecting a crystal, because crystal parameters determine the component values requir ed to provide max imum stability and reliable start-up. the crystal and a ssociated components shoul d be mounted as close as possible to the extal and xtal pins to minimi ze output distortion a nd start-up stabilization time. the internal 56f80x oscillator circuitry is designed to have no external lo ad capacitors present. as shown in figure 3-8 no external load capac itors should be used. the 56f80x components internally are modeled as a pa rallel resonant oscillator circuit to provide a capacitive load on each of the osci llator pins (xtal and extal) of 10pf to 13pf over temperature and process variations. using a typical value of internal capacitance on these pins of 12pf and a value of 3pf as a typical circuit board trace capaci tance the parallel load capacitance presented to the crystal is 9pf as determined by the following equation: this is the value load capacitance that should be us ed when selecting a crysta l and determining the actual frequency of operation of the crystal oscillator circuit. figure 3-7 connecting to a crystal oscillator cl = cl1 * cl2 cl1 + cl2 + cs = + 3 = 6 + 3 = 9pf 12 * 12 12 + 12 recommended external crystal parameters: r z = 1 to 3 m f c = 8mhz (optimized for 8mhz) extal xtal r z f c
56F803 technical data, rev. 16 28 freescale semiconductor 3.5.2 ceramic resonator it is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the re duced signal integrity. in figure 3-8 , a typical ceramic resonator circuit is shown. refer to supplier?s recomm endations when selecting a cer amic resonator and associated components. the resonator and components should be mounted as close as pos sible to the extal and xtal pins. the internal 56f80x osc illator circuitry is designed to have no external load capacitors present. as shown in figure 3-7 no external load capacitors should be used. figure 3-8 connecting a ceramic resonator note: freescale recommends only two terminal cera mic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground). 3.5.3 external clock source the recommended method of connecting an external clock is given in figure 3-9 . the external clock source is connected to xtal and the extal pin is grounded. figure 3-9 connecting an external clock signal recommended ceramic resonator parameters: r z = 1 to 3 m f c = 8mhz (optimized for 8mhz) extal xtal r z f c 56F803 xtal extal external v ss clock
external clock operation 56F803 technical data, rev. 16 freescale semiconductor 29 figure 3-10 external clock timing table 3-8 external clock op eration timing requirements 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c characteristic symbol min typ max unit frequency of operation (external clock driver) 1 1. see figure 3-9 for details on using the recommended co nnection of an external clock driver. f osc 0?80mhz clock pulse width 2 , 3 2. the high or low pulse width must be no smaller than 6.25ns or the chip will not function. however, the high pulse width does not have to be any particular percent of the low pulse width. 3. parameters listed are guaranteed by design. t pw 6.25 ? ? ns external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw
56F803 technical data, rev. 16 30 freescale semiconductor 3.5.4 phase locked loop timing 3.6 external bus asynchronous timing table 3-9 pll timing operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c characteristic symbol min typ max unit external reference cryst al frequency for the pll 1 1. an externally supplied reference cl ock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8mhz input crystal. 2. zclk may not exceed 80mhz. for additional information on zclk and f out /2, please refer to the occs chapter in the user manual. zclk = f op 3. this is the minimum time required after the pll set-up is changed to ensure reliable operation. f osc 4810mhz pll output frequency 2 f out /2 40 ? 110 mhz pll stabilization time 3 0 o to +85 o c t plls ?110ms pll stabilization time 3 -40 o to 0 o c t plls ? 100 200 ms table 3-10 external bus asynchronous timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit address valid to wr asserted t awr 6.5 ? ns wr width asserted wait states = 0 wait states > 0 t wr 7.5 (t*ws) + 7.5 ? ? ns ns wr asserted to d0?d15 out valid t wrd ?4.2ns data out hold time from wr deasserted t doh 4.8 ? ns data out set up time to wr deasserted wait states = 0 wait states > 0 t dos 2.2 (t*ws) + 6.4 ? ? ns ns rd deasserted to address not valid t rda 0?ns address valid to rd deasserted wait states = 0 wait states > 0 t ardd 18.7 (t*ws) + 18.7 ? ns ns
external bus asynchronous timing 56F803 technical data, rev. 16 freescale semiconductor 31 input data hold to rd deasserted t drd 0?ns rd assertion width wait states = 0 wait states > 0 t rd 19 (t*ws) + 19 ? ? ns ns address valid to input data valid wait states = 0 wait states > 0 t ad ? ? 1 (t*ws) + 1 ns ns address valid to rd asserted t arda -4.4 ? ns rd asserted to input data valid wait states = 0 wait states > 0 t rdd ? ? 2.4 (t*ws) + 2.4 ns ns wr deasserted to rd asserted t wrrd 6.8 ? ns rd deasserted to rd asserted t rdrd 0?ns wr deasserted to wr asserted t wrwr 14.1 ? ns rd deasserted to wr asserted t rdwr 12.8 ? ns table 3-10 external bus asynchronous timing 1, 2 (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit
56F803 technical data, rev. 16 32 freescale semiconductor figure 3-11 external bu s asynchronous timing 3.7 reset, stop, wait, mode select, and interrupt timing 1. timing is both wait state and frequency dependent. in the fo rmulas listed, ws = the number of wait states and t = clock period. for 80mhz operation, t = 12.5ns. 2. parameters listed are guaranteed by design. to calculate the required access time for an external memory for any frequency < 80mhz, use this formula: top = clock period @ desired operating frequency ws = number of wait states memory access time = (top*ws) + (top- 11.5) table 3-11 reset, stop, wait, mode select, and in terrupt timing 1, 5 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min max unit see figure reset assertion to address, data and control signals high impedance t raz ?21ns figure 3-12 minimum reset assertion duration 2 omr bit 6 = 0 omr bit 6 = 1 t ra 275,000t 128t ? ? ns ns figure 3-12 reset de-assertion to first external address output t rda 33t 34t ns figure 3-12 a0?a15, ps , ds (see note) wr d0?d15 rd note: during read-modify-write instructions and intern al instructions, the address lines do not change state. data in data out t awr t arda t ardd t rda t rd t rdrd t rdwr t wrwr t wr t dos t wrd t wrrd t ad t doh t drd t rdd
reset, stop, wait, mode select, and interrupt timing 56F803 technical data, rev. 16 freescale semiconductor 33 edge-sensitive interrupt request width t irw 1.5t ? ns figure 3-13 irqa , irqb assertion to exte rnal data memory access out valid, caused by first instruction execution in the interrupt service routine t idm 15t ? ns figure 3-14 irqa , irqb assertion to gene ral purpose output valid, caused by first instruction execution in the interrupt service routine t ig 16t ? ns figure 3-14 irqa low to first valid interrupt vector address out recovery from wait state 3 t iri 13t ? ns figure 3-15 irqa width assertion to recover from stop state 4 t iw 2t ? ns figure 3-16 delay from irqa assertion to fetch of first instruction (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t if ? ? 275,000t 12t ns ns figure 3-16 duration for level sensitive irqa assertion to cause the fetch of first irqa interrupt instru ction (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t irq ? ? 275,000t 12t ns ns figure 3-17 delay from level sensitive irqa assertion to first interrupt vector address out valid (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t ii ? ? 275,000t 12t ns ns figure 3-17 1. in the formulas, t = clock cycle. for an operating frequency of 80mhz, t = 12.5ns. 2. circuit stabilization delay is required during reset when using an external cloc k or crystal oscillator in two cases: ? after power-on reset ? when recovering from stop state 3. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the stop state. this i s not the minimum required so that the irqa interrupt is accepted. 4. the interrupt instruction fetch is visible on the pins only in mode 3. 5. parameters listed are guaranteed by design. table 3-11 reset, stop, wait, mode se lect, and interrupt timing (continued) 1, 5 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min max unit see figure
56F803 technical data, rev. 16 34 freescale semiconductor figure 3-12 asynchronous reset timing figure 3-13 external interrupt ti ming (negative-edge-sensitive) first fetch a0?a15, d0?d15 ps , ds , rd , wr reset first fetch t ra t raz t rda irqa , irqb t irw
reset, stop, wait, mode select, and interrupt timing 56F803 technical data, rev. 16 freescale semiconductor 35 figure 3-14 external level-s ensitive interrupt timing figure 3-15 interrupt fr om wait state timing figure 3-16 recovery from stop state using asynchronous interrupt timing a0?a15, ps , ds , rd , wr irqa , irqb first interrupt instruction execution a) first interrupt instruction execution general purpose i/o pin irqa , irqb b) general purpose i/o t idm t ig instruction fetch irqa , irqb first interrupt vector a0?a15, ps , ds , rd , wr t iri not irqa interrupt vector irqa a0?a15, ps , ds , rd , wr first instruction fetch t iw t if
56F803 technical data, rev. 16 36 freescale semiconductor figure 3-17 recovery from stop state using irqa interrupt service 3.8 serial peripheral interface (spi) timing table 3-12 spi timing 1 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit see figure cycle time master slave t c 50 25 ? ? ns ns figures 3-18 , , 3-20 , 3-21 enable lead time master slave t eld ? 25 ? ? ns ns figure 3-21 enable lag time master slave t elg ? 100 ? ? ns ns figure 3-21 clock (sclk) high time master slave t ch 17.6 12.5 ? ? ns ns figures 3-18 , , 3-20 , 3-21 clock (sclk) low time master slave t cl 24.1 25 ? ? ns ns figures 3-18 , , 3-20 , 3-21 data set-up time required for inputs master slave t ds 20 0 ? ? ns ns figures 3-18 , , 3-20 , 3-21 data hold time required for inputs master slave t dh 0 2 ? ? ns ns figures 3-18 , , 3-20 , 3-21 access time (time to data active from high-impedance state) slave t a 4.8 15 ns figure 3-21 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns figure 3-21 instruction fetch irqa a0?a15 ps , ds , rd , wr first irqa interrupt t irq t ii
serial peripheral interface (spi) timing 56F803 technical data, rev. 16 freescale semiconductor 37 figure 3-18 spi master timing (cpha = 0) data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns figures 3-18 , , 3-20 , 3-21 data invalid master slave t di 0 0 ? ? ns ns figures 3-18 , , 3-20 , 3-21 rise time master slave t r ? ? 11.5 10.0 ns ns figures 3-18 , , 3-20 , 3-21 fall time master slave t f ? ? 9.7 9.0 ns ns figures 3-18 , , 3-20 , 3-21 1. parameters listed are guaranteed by design. table 3-12 spi timing 1 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit see figure sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in master msb out bits 14?1 master lsb out ss (input) ss is held high on master t r t f t f t di t ds t di (ref) t dv t ch t dh t c t r t f t r t cl t ch t cl
56F803 technical data, rev. 16 38 freescale semiconductor figure 3-19 spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in master msb out bits 14? 1 master lsb out ss (input) ss is held high on master t c t cl t f t di t dv (ref) t dv t r t dh t ds t r t ch t ch t cl t f t r t f
serial peripheral interface (spi) timing 56F803 technical data, rev. 16 freescale semiconductor 39 figure 3-20 spi slave timing (cpha = 0) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 msb in bits 14?1 lsb in ss (input) slave lsb out t elg t f t r t c t cl t ch t cl t eld t a t ch t r t f t d t di t di t ds t dh t dv
56F803 technical data, rev. 16 40 freescale semiconductor figure 3-21 spi slave timing (cpha = 1) 3.9 quad timer timing table 3-13 timer timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit timer input period p in 4t+6 ? ns timer input high/low period p inhl 2t+3 ? ns timer output period p out 2t ? ns sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 msb in bits 14?1 lsb in ss (input) slave lsb out t c t cl t dv t a t eld t r t f t elg t ch t cl t ch t f t ds t dv t di t dh t d t r
quadrature decoder timing 56F803 technical data, rev. 16 freescale semiconductor 41 figure 3-22 timer timing 3.10 quadrature decoder timing timer output high/low period p outhl 1t ? ns 1. in the formulas listed, t = clock cycle. for 80mhz operation, t = 12.5ns. 2. parameters listed are guaranteed by design. table 3-14 quadrature decoder timing 1,2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz 1. in the formulas listed, t = clock cy cle. for 80mhz operation, t = 12. ns. v ss = 0 v, v dd = 3.0 ? 3.6v, t a = ?40 to +85 c, c l 50pf. 2. parameters listed are guaranteed by design. characteristic symbol min max unit quadrature input period p in 8t+12 ? ns quadrature input high/low period p hl 4t+6 ? ns quadrature phase period p ph 2t+3 ? ns table 3-13 timer timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz timer inputs timer outputs p in p inhl p inhl p out p outhl p outhl
56F803 technical data, rev. 16 42 freescale semiconductor figure 3-23 quadrature decoder timing 3.11 serial communication interface (sci) timing figure 3-24 rxd pulse width table 3-15 sci timing 4 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max *2.5)/(80) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns phase b (input) phase a (input) p in p in p hl p hl p hl p hl p ph p ph p ph p ph rxd sci receive data pin (input) rxd pw
analog-to-digital converter (adc) characteristics 56F803 technical data, rev. 16 freescale semiconductor 43 figure 3-25 txd pulse width 3.12 analog-to-digital c onverter (adc) characteristics table 3-16 adc characteristics characteristic symbol min typ max unit adc input voltages v adcin 0 1 ? v ref 2 v resolution r es 12 ? 12 bits integral non-linearity 3 inl ? +/- 2.5 +/- 4 lsb 4 differential non-linear ity dnl ? +/- 0.9 +/- 1 lsb 4 monotonicity guaranteed adc internal clock 5 f adic 0.5 ? 5 mhz conversion range r ad v ssa ?v dda v power-up time t adpu ?16 ? t aic cycles 6 conversion time t adc ?6 ? t aic cycles 6 sample time t ads ?1 ? t aic cycles 6 input capacitance c adi ?5 ? pf 6 gain error (transfer gain) 5 e gain 0.95 1.00 1.10 ? offset voltage 5 v offset -80 -15 +20 mv total harmonic distortion 5 thd 60 64 ? db signal-to-noise plus distortion 5 sinad 55 60 ? db effective number of bits 5 enob 9 10 ? bit spurious free dynamic range 5 sfdr 65 70 ? db bandwidth bw ? 100 ? khz txd sci receive data pin (input) txd pw
56F803 technical data, rev. 16 44 freescale semiconductor 1. parasitic capacitance due to package, pin to pi n, and pin to package base coupling. (1.8pf) 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing. (2.04pf) 3. equivalent resistance for the esd isolation resistor and the channel select mux. (500 ohms) 4. sampling capacitor at the sample and hold circuit. (1pf) figure 3-26 equivalent an alog input circuit 3.13 controller area network (can) timing adc quiescent current (both adcs) i adc ?50 ? ma v ref quiescent current (both adcs) i vref ?12 16.5 ma 1. for optimum adc performance, keep the minimum v adcin value > 25mv. inputs less than 25mv may convert to a digital output code of 0. 2. v ref must be equal to or less than v dda and must be greater than 2.7v. for optimal adc performance, set v ref to v d- da -0.3v. 3. measured in 10-90% range. 4. lsb = least significant bit. 5. guaranteed by characterization. 6. t aic = 1/ f adic table 3-17 can timing 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85c, c l 50pf, mscan clock = 30mhz characteristic symbol min max unit baud rate br can ?1mbps bus wakeup detection 1 t wakeup 5? s table 3-16 adc characteristics characteristic symbol min typ max unit 1 2 3 4 adc analog input
controller area network (can) timing 56F803 technical data, rev. 16 freescale semiconductor 45 figure 3-27 bus wakeup detection 1. if wakeup glitch filter is enabled during the design initializat ion and also can is put into sleep mode then, any bus event (on mscan_rx pin) whose duration is less than 5 micro seconds is filtered away. however, a valid can bus wakeup detec- tion takes place for a wakeup pulse equal to or greater than 5 mi croseconds. the value of 5 micr oseconds originates from the fact that the can wakeup message consists of 5 dominant bits at the highest possible baud rate of 1mbps. 2. parameters listed are guaranteed by design. mscan_rx can receive data pin (input) t wakeup
56F803 technical data, rev. 16 46 freescale semiconductor 3.14 jtag timing figure 3-28 test clock input timing diagram table 3-18 jtag timing 1, 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 80mhz operation, t = 12.5ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/8 the processor rate. 3. parameters listed are guaranteed by design. f op dc 10 mhz tck cycle time t cy 100 ? ns tck clock pulse width t pw 50 ? ns tms, tdi data set-up time t ds 0.4 ? ns tms, tdi data hold time t dh 1.2 ? ns tck low to tdo data valid t dv ? 26.6 ns tck low to tdo tri-state t ts ? 23.5 ns trst assertion time t trst 50 ? ns de assertion time t de 4t ? ns tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t cy t pw
jtag timing 56F803 technical data, rev. 16 freescale semiconductor 47 figure 3-29 test access po rt timing diagram figure 3-30 trst timing diagram figure 3-31 once?debug event input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t ts t dv t ds t dh trst (input) t trst de t de
56F803 technical data, rev. 16 48 freescale semiconductor part 4 packaging 4.1 package and pin-out information 56F803 this section contains package and pin-out information for the 100-pin lqfp configuration of the 56F803. figure 4-1 top view, 56f 803 100-pin lqfp package pin 1 pin 26 pin 51 pin 76 d10 d11 d12 d13 d14 d15 a0 v dd v ss a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 v dd ps ds a14 a15 v ss wr rd irqa irqb tcs tck tms tdi tdo trst vcapc isa0 isa1 isa2 faulta0 mscan_tx faulta1 mscan_rx faulta2 vref an0 an1 pwma5 pwma4 pwma3 pwma2 pwma1 pwma0 home0 index0 v ss v dd phaseb0 phasea0 v ss v dd v dd v dda v ssa extal xtal an7 an6 an5 an4 an3 an2 d9 d8 d7 d6 d5 d4 d3 v ss v dd d2 d1 d0 vcapc sclk mosi miso ss td2 td1 clko de reset extboot rxd0 txd0 orientation mark
package and pin-out information 56F803 56F803 technical data, rev. 16 freescale semiconductor 49 table 4-1 56F803 pin iden tification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 d10 26 a14 51 an2 76 txd0 2 d11 27 a15 52 an3 77 rxd0 3 d12 28 v ss 53 an4 78 extboot 4 d13 29 wr 54 an5 79 reset 5 d14 30 rd 55 an6 80 de 6 d15 31 irqa 56 an7 81 clko 7a032irqb 57 xtal 82 td1 8v dd 33 tcs 58 extal 83 td2 9v ss 34 tck 59 v ssa 84 ss 10 a1 35 tms 60 v dda 85 miso 11 a2 36 tdi 61 v dd 86 mosi 12 a3 37 tdo 62 v dd 87 sclk 13 a4 38 trst 63 v ss 88 vcapc 14 a5 39 vcapc 64 phasea0 89 d0 15 a6 40 isa0 65 phaseb0 90 d1 16 a7 41 isa1 66 v dd 91 d2 17 a8 42 isa2 67 v ss 92 v dd 18 a9 43 faulta0 68 index0 93 v ss 19 a10 44 mscan_tx 69 home0 94 d3 20 a11 45 faulta1 70 pwma0 95 d4 21 a12 46 mscan_rx 71 pwma1 96 d5 22 a13 47 faulta2 72 pwma2 97 d6 23 v dd 48 vref 73 pwma3 98 d7 24 ps 49 an0 74 pwma4 99 d8 25 ds 50 an1 75 pwma5 100 d9
56F803 technical data, rev. 16 50 freescale semiconductor figure 4-2 100-pin lqpf m echanical information notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350 (0.014). dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.070 (0.003). 8. minimum solder plate thickness shall be 0.0076 (0.003). 9. exact shape of each corner may vary from depiction. ae ae ad seating (24x per side) r gauge plane detail ad section ae-ae s v b a 96x x e c k h w d f j n 9 dim min max min max inches millimeters a 13.950 14.050 0.549 0.553 b 13.950 14.050 0.549 0.553 c 1.400 1.600 0.055 0.063 d 0.170 0.270 0.007 0.011 e 1.350 1.450 0.053 0.057 f 0.170 0.230 0.007 0.009 g 0.500 bsc 0.020 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 q 1 5 1 5 r 0.150 0.250 0.006 0.010 s 15.950 16.050 0.628 0.632 v 15.950 16.050 0.628 0.632 w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref -t- s t-u s 0.15 (0.006) z s ac s t-u s 0.15 (0.006) z s ac s t-u s 0.15 (0.006) z s ac -u- s t-u s 0.15 (0.006) z s ab -z- -ac- g plane -ab- s t-u m 0.20 (0.008) z s ac 0.100 (0.004) ac q m 0.25 (0.010)
thermal design considerations 56F803 technical data, rev. 16 freescale semiconductor 51 please see www.freescale.com for the most current case outline. part 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature c r ja = package junction-to-ambie nt thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a j unction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r ja = package junction-to-ambie nt thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and ca nnot be influenced by the user. the user controls the thermal environment to change the case-to-ambien t thermal resistance, r ca . for example, the user ca n change the air flow around the device, add a heat sink, change the mounting ar rangement on the printed circuit board (pcb), or otherwise change the thermal diss ipation capability of the area su rrounding the device on the pcb. this model is most useful for ceramic pa ckages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for cera mic packages, in situations where the heat flow is split between a path to the case a nd an alternate path through the pcb, analysis of the device thermal performance may need the additional modeli ng capability of a sy stem level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperat ure of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a sy stem level model may be appropriate. definitions: a complicating factor is the existe nce of three common definitions fo r determining the junction-to-case thermal resistance in plastic packages: ? measure the thermal resistance from the junction to th e outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation t j t a p d r ja () + = r ja r jc r ca + =
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